Associate CET · Competency 13.x — Digital

🔢 Digital / Logic Calculator

The number-crunching side of digital electronics: convert between bases, decode two's-complement signed numbers, pack BCD, simplify Boolean expressions, and work out counter / flip-flop frequency division. Built to match the Associate CET exam digital competencies.

Number Base Converter

Type a value in any base and see it in all the others instantly. Toggle individual bits in the bit view to build a number by hand — great for understanding place value.

Decimal value

BCD note: Binary-Coded Decimal stores each decimal digit in its own 4-bit group (so 170 → 0001 0111 0000). It wastes bits but makes driving decimal displays trivial. It is not the same as plain binary.

Two's-Complement Signed Numbers

Two's complement is how computers store negative integers. Enter a signed decimal to encode it, or a binary pattern to decode it. Pick the word width below.

Signed decimal → binary

Binary pattern → decimal

Quick method: to negate a two's-complement number, invert all the bits then add 1. The most-significant bit is the sign bit: 1 means negative. An 8-bit value covers −128 to +127.

Boolean Expression Analyzer

Enter a Boolean expression using variables A–D. Use * or . or & for AND, + or | for OR, ! or ' or ~ for NOT, and ^ for XOR. The tool builds the full truth table and finds a simplified sum-of-products form.

Expression

Tip: the simplified form shown is a minimal sum-of-products (SOP) derived from the truth table. A*B + A*!B simplifies to just A, since B drops out — a classic example of Boolean reduction.

Counter / Flip-Flop Frequency Divider

Each flip-flop stage divides the clock frequency by 2. A chain of n stages divides by 2ⁿ and can count 2ⁿ states. You can also set a custom modulus (e.g. a divide-by-10 decade counter).

f_out = f_in / N (ripple counter: N = 2ⁿ)

Input clock frequency

MHz

Frequency unit

Mode

Number of stages (n)

Worked idea: a 4-stage binary ripple counter divides by 2⁴ = 16 and counts 0–15. A 555 or crystal feeding a divide-by-2⁴ chain at 32.768 kHz gets you toward the classic 1 Hz clock tick after 15 stages (÷32768).